Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ames!oliveb!pyramid!prls!philabs!linus!nixbur!nixpbe!peun39!bfranke
From: bfranke@peun39.UUCP
Newsgroups: comp.arch
Subject: Re: 386/486 Virtual Memory Question...
Message-ID: <48000001@peun39>
Date: 12 Jun 89 20:25:03 GMT
References: <1078200856@andrew.cmu.edu>
Lines: 32
Nf-ID: #R:andrew.cmu.edu:1078200856:peun39:48000001:000:1216
Nf-From: peun39.UUCP!bfranke    Jun 12 17:12:00 1989


/* Written  9:36 pm  Jun  6, 1989 by hs0l+@andrew.cmu.edu.UUCP in peun39:comp.arch */
/* ---------- "386/486 Virtual Memory Question..." ---------- */

The 386 and 486 architectures claim a virtual address space size of
2^46 bytes.  The virtual address is formed from a 14 bit selector
and a 32 bit offset.  What does this really mean?  Currently we have
two interpretations:

	a) This scheme gives us 2^14 different ways to map into
	   the same 32 bit address space.

	b) This scheme gives us 2^14 independent address spaces
	   of 2^32 bytes each.  In other words, the virtual memory
	   scheme consists of as many as 2^14 segments of 2^32
	   bytes each.

Which one is the correct interpretation?  If (a) is the answer, why was
it done this way?  If (b) is the answer, how does the processor
communicate
the 14 bits of selector information to the memory mapping
hardware/software?

I think (b) is the correct answer, but after spending a few minutes with
some Intel literature, I'm more confused than I was when I started.
Any comments would be appreciated.  Thanks.

Brinkley Sprunt
Elecetical & Computer Engineering
Carnegie Mellon University
sprunt@maxwell.ece.cmu.edu
/* End of text from peun39:comp.arch */