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From: winter@doomb.prl.philips.nl (Pieter Winter)
Newsgroups: comp.arch
Subject: Re: RISC list
Keywords: risc, list
Message-ID: <522@prles2.UUCP>
Date: 16 Jun 89 06:48:16 GMT
References: <1173@cbnewsc.ATT.COM> <1989Jun14.223902.12665@ziebmef.uucp>
Sender: nobody@prles2.UUCP
Reply-To: winter@doomb.prl.philips.nl (Pieter Winter)
Organization: Philips Research Labs Eindhoven
Lines: 29

In article <1989Jun14.223902.12665@ziebmef.uucp> mcp@ziebmef.UUCP (Colin Plumb) writes:
>Not to beat up on a chip I've worked on, but the Transputer is pretty
>much the opposite of most RISC chips.  Lessee... very few registers,
>an instruction set designed for a naive compiler, tons of microcode,
>and an instruction set that's hard to pigeonhole, but is optimised for
>static code density and behaves a lot like it has variable-length
>instructions.
>
>*Everyone* has stolen *some* ideas from the RISC movement, but I don't
>think this appelation is justified.  Whatever the marketroids say.
>-- 
>	-Colin Plumb

This might be my mistake, but I was under the impression that the Transputer
*does* have a RISC instruction set (few operations, and with an option of
shifting bits up to 32?), and that the microcode does not only provide the
user with the instructions, but also provides proces scheduling and i/o
fascilities?? :-)

I don't know anything about the registers, because I never actually programmed
a transputer.

Pieter

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- Pieter Winter				winter@doomb.prl.philips.nl           -
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- No man in his right mind...(?), left mind...(?), Ehhhh...(!), Nobody minds! -
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