Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!versatc!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: TRON (a little long) Keywords: Japan, TRON, standards, networks, operating systems Message-ID: <21768@winchester.mips.COM> Date: 16 Jun 89 17:34:27 GMT References: <382@h.cs.wvu.wvnet.edu> <4567@ficc.uu.net> <25518@agate.BERKELEY.EDU> Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 12 Since this is comp.arch, how about whoever started this, or somebody, post a brief description of the TRON instruction set architecture. There was one in IEEE Computer or Micro a while back. At least, let's keep the part of this in comp.arch having something to do with architecture, and that might deal with facts instead of random speculations. -- -john mashey DISCLAIMER: UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086