Xref: utzoo comp.std.misc:120 comp.realtime:84 comp.arch:10297 comp.os.misc:934 comp.misc:6356
Path: utzoo!attcan!uunet!cs.utexas.edu!ico!ism780c!news
From: news@ism780c.isc.com (News system)
Newsgroups: comp.std.misc,comp.realtime,comp.arch,comp.os.misc,comp.misc
Subject: Re: TRON (a little long)
Keywords: Japan, TRON, standards, networks, operating systems
Message-ID: <28643@ism780c.isc.com>
Date: 16 Jun 89 20:33:21 GMT
References: <5117@stiatl.UUCP>
Reply-To: marv@ism780.UUCP (Marvin Rubenstein)
Organization: Interactive Systems Corp., Santa Monica CA
Lines: 35

In article <5117@stiatl.UUCP> meo@stiatl.UUCP (Miles O'Neal) writes:
>But also, there has not been very much press coverage, or professional
>group attention turned towards it. I suspect most of us don't really
>even know what all it covers. I certainly don't. Throw in that with the
>fact that we are standardizing on UNIX (the ultimate real-time system
>(haha)) and a handful of microprocessors, and most people see no need,
>no interest, no threat.
>
>SO, educate us. What are the high points, the low points, and such,
>from your vantage point?

We are just finishing a Unix port to the H32/200 one of the chips in the
TRON family.  What I can tell you is that it is the ULTIMATE CISC machine.

Here is a single assembly source instruction:

     mov @(@(@(@(100000,r1),300000,r2),400000,r3),500000,r4),\
	 @(@(@(@(100000,r1),300000,r2),400000,r3),500000,r4)

And here is the resulting object instruction.

	 D20B 4412 0001 86A0
         4812 0004 93E0 4C12 
         0006 1A80 9012 0007 
         A120 8A0B 4412 0001 
         86A0 4812 0004 93E0 
         4C12 0006 1A80 9012 
         0007 A120           

This single instruction perfoms 8 memory accesses for address computation and
two more accesses to move data.  And it is possible to write an instruction
even longer than this one.  Needless to say, the compiler that I wrote does
not make use of all the possible address modes.

    Marv Rubinstein