Path: utzoo!attcan!uunet!portal!cup.portal.com!mslater
From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Re: FPU chip set
Message-ID: <19575@cup.portal.com>
Date: 17 Jun 89 17:23:23 GMT
References: <871@stag.UUCP>
Organization: The Portal System (TM)
Lines: 15

> ECL FPU from BIT

BIT recently introduced their ECL SPARC chip set, which uses some ECL
FPU components.  The SPARC IU and floating-point coprocessor are new
chips; they work with two FP register file chips, a FP ALU, and an
FP multiplier chip, which have been around for a couple years and are
general-purpose.  I don't know what the FP chips sell for separately,
but the full SPARC chip set is $3300 in 100s; the IU alone is $850.  The SPARC
set is rated at 40 MFLOPS peak, 14 MFLOPS for compiled double-precision
Linpack.  Integer performance is stated as 50 to 65 MIPS; clock rate
is 80 MHz.  Samples are now available, and production is scheduled for
early '90.

Michael Slater, Microprocessor Report      mslater@cup.portal.com
550 California Ave., Suite 320, Palo Alto, CA 94306   415/494-2677