Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!rochester!pt.cs.cmu.edu!andrew.cmu.edu!<UNAUTHENTICATED>+
From: Daniel.Stodolsky@cs.cmu.edu
Newsgroups: comp.arch
Subject: Write-thru  vs. Write-back caches (Was: workstations for LISP)
Message-ID: <8YayEBu00hMN8J1lAJ@cs.cmu.edu>
Date: 18 Jun 89 18:03:57 GMT
Organization: Carnegie Mellon, Pittsburgh, PA
Lines: 9

When memory latency (I/O) dominates in an application, it seems like
write-back caches should be a big win, particularly on single processor
machines where you don't have to worry about cache coherency.

So why don't we see more write-back D-caches? 

Daniel Stodolsky
EDRC
danner@edrc.cmu.edu