Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!cs.utexas.edu!sun-barr!sun!imagen!atari!portal!cup.portal.com!mslater
From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Re: SPARC Implementations
Message-ID: <19629@cup.portal.com>
Date: 18 Jun 89 18:00:11 GMT
References: <351@ctycal.UUCP>
Organization: The Portal System (TM)
Lines: 18

>Can someone explain the basic differences between the Cypress and Fujitsu
>SPARC implementations?  Are they binary code compatible?

They are binary compatible, although the Cypress chip has a couple of
instructions that the Fujitsu does not.

There are two Fujitsu chips: the original gate array, now called the
S-16, which runs at 16 MHz, and a standard-cell reimplementation, called
the S-20 and S-25, at 20 and 25 MHz.  The Cypress chip is a full-custom
design, and runs at up to 33 MHz.  All three designs have different
pinouts.  The Cypress design has a different hardware structure for the
coprocessor interface.

All of these designs are pretty primitive -- No on-chip floating-point,
MMU, or cache control.  Things will get more interesting in the next
generation.

Michael Slater, Microprocessor Report   mslater@cup.portal.com