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From: SFurber@acorn.co.uk
Newsgroups: comp.arch
Subject: Caches
Message-ID: <799@acorn.co.uk>
Date: 20 Jun 89 08:46:11 GMT
Sender: sfurber@acorn.co.uk
Lines: 19


Daniel Stodolsky writes:

> When memory latency (I/O) dominates in an application, it seems like
> write-back caches should be a big win, particularly on single processor
> machines where you don't have to worry about cache coherency.
>
> So why don't we see more write-back D-caches? 

A write buffer fixes the memory latency problem; a write-back cache is
needed only if memory bandwidth is also an issue.

At first sight a write buffer looks a lot simpler to build than a write-back
cache, because of the flushing issues involved in context switching or
paging with the latter. However Jouppi (Proceedings of 16th International
Symposium on Computer Architecture, p. 287) states that for similar
performance "A write-back cache is a simpler design...".

Steve Furber (sfurber@acorn.uucp)