Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!sun-barr!sun!imagen!atari!portal!cup.portal.com!mslater
From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Re: FPU chip set
Message-ID: <19706@cup.portal.com>
Date: 20 Jun 89 17:47:24 GMT
References: <871@stag.UUCP> <12111@polyslo.CalPoly.EDU>
Organization: The Portal System (TM)
Lines: 23

>   Reads like a good implementation of SPARC has shown up. One thing I am
>troubled by is the cache memory set-up. I am completely un-bothered by
>the need for a second-level cache. However, I am worried that the
>primary level (closest to the CPU) has its architecture pre-defined by
>the chip builders, ie. I don't get to tweak the design of the cache (if
>I ever decide to work with this stuff). "Say it isn't so."

It isn't so.  BIT provides no cache support, giving you the freedom to
do whatever you want for the first-level cache.  On the other hand, this
gives you the obligation to figure out how to build a 12-ns cache system.

The only cache limitation is that the IU provides separate address lines
for the cache that are clocked earlier in the cycle, and these lines
support a maximum of 512 Kbytes of cache.  Given the cost of the 8-ns RAMs
you need to build this cache, that size limitation shouldn't be much of a
problem.

BIT admits that the system designer will have to build a few ASICs to make
the cache and MMU.  It will be interesting to see how the MIPS ECL design
handles this.

Michael Slater, Microprocessor Report     mslater@cup.portal.com
550 California Ave., Suite 320, Palo Alto, CA 94306   415/494-2677