Xref: utzoo comp.arch:10371 misc.wanted:5340 comp.sources.wanted:7829
Newsgroups: comp.arch,misc.wanted,comp.sources.wanted
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: MIPS Assembler Procedure
Message-ID: <1989Jun24.230056.27774@utzoo.uucp>
Organization: U of Toronto Zoology
References: <57125@linus.UUCP>
Date: Sat, 24 Jun 89 23:00:56 GMT

In article <57125@linus.UUCP> bs@gauss.UUCP (Robert D. Silverman) writes:
>This, in my opinion is one of the major faults of RISC processors. They
>do not provide basic arithmetic instructions. 

When the list of "basic" arithmetic instructions is pages long, one starts
to wonder how many of them are really "basic".  The instruction you ask
for -- divide double length by single length yielding single-length result --
is not exactly frequently needed.  Just how much silicon is it worth to make
it run faster than an implementation as a subroutine?
-- 
NASA is to spaceflight as the  |     Henry Spencer at U of Toronto Zoology
US government is to freedom.   | uunet!attcan!utzoo!henry henry@zoo.toronto.edu