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From: rajgopal@lhotse.cs.unc.edu (Suresh Rajgopal)
Newsgroups: comp.lsi
Subject: Re: Transistor sizing
Message-ID: <8556@thorin.cs.unc.edu>
Date: 20 Jun 89 16:19:54 GMT
References: <2579@daimi.dk>
Sender: news@thorin.cs.unc.edu
Reply-To: rajgopal@lhotse.cs.unc.edu (Suresh Rajgopal)
Organization: University Of North Carolina, Chapel Hill
Lines: 25

In article <2579@daimi.dk> svendsen@daimi.dk (Erik Svendsen) writes:
>
>
>	Has anybody got some good references on optimal transistor
>	sizing in VLSI circuits (CMOS)?
>
  A tool for automated transistor sizing (AESOP) has been 
 developed here at UNC-Chapel Hill. If interested, I would suggest you
get in touch with Prof. Kye Hedlund  (hedlund@cs.unc.edu) here
in the Computer Science Deptt. He could
probably indicate  other references.

-Suresh

>
>		Erik Svendsen                      e-mail: svendsen@daimi.dk
>
>                                                        
>  Erik Svendsen, Peder Skrams Gade 58 3 tv, DK-8200 Aarhus N, Danmark.
>  telephone: +45 6 10 10 96


   Suresh Rajgopal  rajgopal@dopey.cs.unc.edu  uunet!mcnc!unc!rajgopal
    "To search for perfection is all very well,
      But to look for heaven is to live here in hell"