Path: utzoo!attcan!uunet!cs.utexas.edu!tut.cis.ohio-state.edu!ucsd!ames!ncar!noao!asuvax!behemoth!mph
From: mph@behemoth.phx.mcd.mot.com (Mark Huth)
Newsgroups: comp.sys.amiga
Subject: Re: GVP 68030 reviewed in Sentry
Message-ID: <11085@behemoth.phx.mcd.mot.com>
Date: 14 Jun 89 21:07:36 GMT
References: <11044@mcdphx.phx.mcd.mot.com> <7083@cbmvax.UUCP>
Reply-To: mph@behemoth.UUCP (Mark Huth)
Distribution: na
Organization: Motorola Microcomputer Division, Tempe, Az.
Lines: 23

In article <7083@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes:
>in article <11044@mcdphx.phx.mcd.mot.com>, dbk@teroach.UUCP (Dave Kinzer) says:
>Well, yes and no.  The caches on both '030 and '020 are straight mapped 256
>byte caches.  They're organized a bit differently, the '030 caches are both
>16 entries of 4 longword lines, I don't recall the exact organization of
>the '020 cache.  Minimally, though, in either case you overwrite a cache
>entry by accessing an item on the same (address % 256) location.  So if you

There are 64 cache lines in the '020 instruction cache.  Instructions with
a different tag for each longword (64 all together) must be fetched - not
necessarily executed to ensure that the cache has been invalidated with regard
to previous cache contents.  This is quite common, and it should be possible
to determine that the execution of a particular piece of code will overwrite
the cache, probably removing the need to invalidate the '020 instruction cache.

The '030 caches have been reorganized into 16 line by 4 longword organization
in order to allow burst fill operation.  In this mode, given a properly
designed memory system, the first memory cycle may require a minimum of two
clock cycles, and the next three sequential locations may require a minimum
of 1 additional clock cycle for each longword.  DRAM chips with nibble modes
support this type of operation.

Mark Huth