Path: utzoo!attcan!ncrcan!ziebmef!mcp
From: mcp@ziebmef.uucp (Marc Plumb)
Newsgroups: comp.sys.amiga
Subject: Re: enhanced chip set
Message-ID: <1989Jun19.013022.17567@ziebmef.uucp>
Date: 19 Jun 89 05:30:20 GMT
References: <11185@orstcs.CS.ORST.EDU>
Reply-To: mcp@ziebmef.UUCP (Colin Plumb)
Distribution: na
Organization: Ziebmef Public Access Unix, Toronto, Ontario
Lines: 20

I just got a copy of the DevCon stuff... in the new chip set:
Bigger blits (up to 32Kx32K)
1 Meg Chip
Super-hires mode (4 colours, 6 bits/colour (2R, 2G, 2B), 1280 pixels/line)
"Productivity mode" double-speed non-interlaced scanning
  (pixels are twice as fat, so you need to use super-hi-res to get 640
  pixels across)
Genlock any set of colours as transparent, and the border is independently
  selectable.  You can also use a separate bitplane to select opacity.
The documented hardware stop that stops you from overscanning onto
  sprites 0 and 1 now actually exists.
There are a lot of neat ways to program the various blanking intervals.
  One particularly interesting register comes with a warning:
  "Incorrect doftware writing to the BEAMCON0 has the (remote) chance of
  destroying your extremely expensive multisync monitor."

There's lots of support in the 1.4 graphics.library for all this.  The 2024
(Viking/Hedeley) monitor, etc.  Looks good!
-- 
	-Colin