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From: m5@lynx.uucp (Mike McNally)
Newsgroups: comp.unix.wizards
Subject: Re: Information on SPARC assembly (atomic Test and Set)
Message-ID: <5742@lynx.UUCP>
Date: 19 Jun 89 17:00:54 GMT
References: <350@osc.COM> <577@lakart.UUCP>
Reply-To: m5@lynx.UUCP (Mike McNally)
Organization: Lynx Real-Time Systems Inc, Campbell CA
Lines: 27

In article <577@lakart.UUCP> dg@lakart.UUCP (David Goodenough) writes:
>I have never understood the need for a test and set instruction, when
>you can make do with adc (add with carry). Allow me to explain:
>
>The point behind TAS is to allow a process to test if a flag is set or
>clear, and set it no matter what the result. But why does the test have
>to be in the same instruction? 

The example given by Mr. Goodenough in fact incorporates the changing of 
the state of the flag in one instruction (the add-with-carry).  It is
thus true that the sequence is unbreakable *at the OS level*: a normal
OS will not reschedule while a task is in the middle of an instruction,
because most CPU's won't allow interrupts in the middle of an instruction.
(Note that this is not necessarily the case.)  A real TAS instruction
often comes with the proviso that the bus cycles used to fetch and store
are not interruptable either.  This guarantee is necessary in a multi-
processor environment.

I think that the x86 (x>0) series locks the bus on all XCHG instructions.
The original chips required a LOCK prefix.  I don't know whether or not
the LOCK is honored with other read/write instructions.

-- 
Mike McNally                                    Lynx Real-Time Systems
uucp: {voder,athsys}!lynx!m5                    phone: 408 370 2233

            Where equal mind and contest equal, go.