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From: davidsen@sungod.crd.ge.com (William Davidsen)
Newsgroups: comp.unix.wizards
Subject: Re: Information on SPARC assembly (atomic Test and Set)
Message-ID: <889@crdgw1.crd.ge.com>
Date: 20 Jun 89 14:56:37 GMT
References: <350@osc.COM> <577@lakart.UUCP> <5742@lynx.UUCP>
Sender: news@crdgw1.crd.ge.com
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Organization: General Electric Corp. R&D, Schenectady, NY
Lines: 16

In article <5742@lynx.UUCP> m5@lynx.UUCP (Mike McNally) writes:

| I think that the x86 (x>0) series locks the bus on all XCHG instructions.
| The original chips required a LOCK prefix.  I don't know whether or not
| the LOCK is honored with other read/write instructions.

  Specified to lock the bus until the next instruction is complete. This
is a reasonable way to allow multiple processors to use any appropriate
interlock. I don't really like the ADDC for flag testing, since some
logic paths may require a loop until free (for short term resources) and
something could overflow.

  Why was this posted to wizards instead of arch????
	bill davidsen		(davidsen@crdos1.crd.GE.COM)
  {uunet | philabs}!crdgw1!crdos1!davidsen
"Stupidity, like virtue, is its own reward" -me