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From: greyham@hades.OZ (Greyham Stoney)
Newsgroups: comp.arch
Subject: 80186 Interrupts: Am I missing something?
Keywords: 80186, Interrupts, Edge-Trigger, Blast, Pow, Sock, Wham.
Message-ID: <258@hades.OZ>
Date: 15 Jun 89 16:49:07 GMT
Organization: Ausonics Pty Ltd, Sydney, Australia
Lines: 42

Hiyall comparchies......

	I have a nasty little problem with an 80186 system I'm working on at
the moment; basically the problem is to do with missing interrupts. The
80186's built-in interrupt controller is being use to handle interrupts
from a variety of sources. Two of them in particular are something of a
worry because they are very short, cannot afford to be missed, and may
occur at almost exactly the same time. The problem seems to be that the
80186 doesn't latch the interrupts when they occur; so with my two
interrupts, if one of them is being serviced when the second comes in, the
second gets lost.

	Some solutions spring to mind:

	* make the second a higher priority than the first, and re-enable
interrupts in the first's service routine. This doesn't work though if they
come in in the reverse order (which they might).

	* make them the same priority and issue an EOI at the start of both
interrupt routines. This screws up though if two of the same interrupt come
in very close together; which they may well do.

	* make the hardware latch the things. Ha!. Only kidding!!!!

	Or is there something I've missed?. Yes, I have as a matter of fact
RTFM'd and if you've done so too, you'll know how much help that was.

	Any help greatly appreciated; EMAIL me direct and I'll summarize to
the net.

		thankyou,
			Greyham


	Great.... now I can get back to slandering some Intel RISC
	based DMA cray 68000 optimisation VAX mainframe front-ends.....

-- 
/*  Greyham Stoney:    +61 2 428 6476
 *     greyham@hades.oz  - Ausonics, Lane Cove, Oz.   <- first preference
 *     greyham@utscsd.oz - Uni of Technology, Sydney. <- if hades bounces
 */	Zero Knowledge: Now THERE'S a concept I can identify with!!!