Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!usc!bloom-beacon!bu-cs!purdue!mentor.cc.purdue.edu!pur-ee!hankd
From: hankd@pur-ee.UUCP (Hank Dietz)
Newsgroups: comp.arch
Subject: Re: Caches
Summary: Another HW alternative, also compiler-controlled HW
Message-ID: <12070@pur-ee.UUCP>
Date: 28 Jun 89 15:44:14 GMT
References: <799@acorn.co.uk> <95@altos86.Altos.COM> <195@dg.dg.com>
Reply-To: hankd@pur-ee.UUCP (Hank Dietz)
Organization: Purdue University Engineering Computer Network
Lines: 34

In article <195@dg.dg.com> rec@dg.UUCP (Robert Cousins) writes:
>In article <95@altos86.Altos.COM> dtynan@altos86.Altos.COM (Dermot Tynan) writes:
>>In article <799@acorn.co.uk>, SFurber@acorn.co.uk writes:
>>> At first sight a write buffer looks a lot simpler to build than a write-back
>>> cache, because of the flushing issues involved in context switching or
>>> paging with the latter. However Jouppi (Proceedings of 16th International
...
>>[Comment wanting proof of lower complexity]
...
>[Comments giving arguments for lower complexity]

Hmmm.  It seems to me that there are at least three, not two, alternatives:
write-through, write-back, and lazy-write.  Using the lazy-write idea, you
have the cache watch for free memory bus cycles and execute a "pending"
entry write whenever it finds a free cycle...  of course, if there are lots
of free cycles this is equivalent to write-through, whereas it is equivalent
to write-back if there are no free cycles.  If you think about it,
lazy-write can be a really big win with only a little more circuitry.  Yes,
lazy-write is MORE circuitry ;-).

>While I tend to view caches as a necessary evil, a truly optimized caching
>scheme is a complex beast.  

Not necessarily complex in hardware.  Making the cache HW be more explicitly
controlled by the compiler is a big win in reducing HW complexity while
reaping big performance gains.  This sounds a lot like the argument for RISC
processors, doesn't it?

The most complete picture is C-H Chi's PhD thesis, "Compiler-Driven Cache
Management Using A State Level Transition Model," Purdue University School
of EE, May 1989...  Chi and I have a number of papers published on this sort
of thing.

						-hankd@ee.ecn.purdue.edu