Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!apple!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: Caches
Message-ID: <42095@bbn.COM>
Date: 28 Jun 89 16:37:26 GMT
References: <799@acorn.co.uk> <95@altos86.Altos.COM> <195@dg.dg.com> <918@m3.mfci.UUCP>
Sender: news@bbn.COM
Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
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In article <918@m3.mfci.UUCP> rodman@mfci.UUCP (Paul Rodman) writes:
>In article <195@dg.dg.com> rec@dg.UUCP (Robert Cousins) writes:
>>At this point, a write through cache seems simpler.  However, if the
>>line size is greater than a single word, the number of states increases
>>[case assuming write-allocate is implemented]
>Not all write-thru caches will require a RMW even if the line size is larger 
>than the word size. Some will store a seperate copy of the tag (or cache 
>index) with each word. 

If the cache does not to allocate-on-write, and the memory supports 
byte-write, the RMW in the cache is not necessary.  ie the bytes written
if a miss don't write the cache, just memory.  This just moves the RMW
to the memory, you may say?  Lots of systems have RMW in the memory
anyway so that I/O can do writes with data sizes smaller than the 
line size.

>Write-back caches are vulnerable to SRAM soft errors.

I've heard of mainframes with ERCC in the cache.

Stan