Xref: utzoo comp.arch:10425 misc.wanted:5379 comp.sources.wanted:7898 Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!uunet!philmtl!philabs!linus!bs From: bs@linus.UUCP (Robert D. Silverman) Newsgroups: comp.arch,misc.wanted,comp.sources.wanted Subject: Re: MIPS Assembler Procedure Message-ID: <57725@linus.UUCP> Date: 26 Jun 89 22:25:50 GMT References: <57125@linus.UUCP> <1989Jun24.230056.27774@utzoo.uucp> <41957@bbn.COM> Reply-To: bs@gauss.UUCP (Robert D. Silverman) Organization: The MITRE Corporation, Bedford MA Lines: 42 In article <41957@bbn.COM> slackey@BBN.COM (Stan Lackey) writes: :In article <1989Jun24.230056.27774@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes: :>In article <57125@linus.UUCP> bs@gauss.UUCP (Robert D. Silverman) writes: :>>This, in my opinion is one of the major faults of RISC processors. They :>>do not provide basic arithmetic instructions. :> :>When the list of "basic" arithmetic instructions is pages long, one starts :>to wonder how many of them are really "basic". The instruction you ask :>for -- divide double length by single length yielding single-length result -- :>is not exactly frequently needed. Just how much silicon is it worth to make :>it run faster than an implementation as a subroutine? : :The RISC suppliers would like us (users) to believe that RISC is :ALWAYS faster. I can't help thinking back to when Patterson's first :RISC papers came out. He managed to tune the code on his RISC until :all of the benchmarks ran faster than the VAX 11/780, except for one, :which happened to exercise one of the microcoded character string :instructions a lot. : :The moral of the story: If your application needs mul and div :performance, get a micro with hardware support for them. If that :means using a CISC, so be it. : :BTW: divide-double-by-single-yielding-single is the one the 68000 :included. Is there a chicken-and-egg situation here? No, to the last question. Such an instruction is required to compute AB/C or AB MOD C exactly, when AB can overflow and C > A,B. The problem with CISC is that no one is likely to come out with a 40MIP CISC in the near future [e.g. i860]. I simply contend that operations like multiplication and division should be fundamental to ANY computer. I also include add, subtract and add/subtract with carry. How else would you compute AB/C or AB % C exactly? Note that I've also seen some pretty arcane instructions on so called RISC processors. The i860 even has a custom purpose piece of real estate on the chip to support special graphics operations. However, it can't multiply or divide!!!! This is RISC? Bob Silverman :-Stan