Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!lll-winken!uunet!philmtl!philabs!linus!munck
From: munck@linus.UUCP (Robert Munck)
Newsgroups: comp.arch
Subject: Re: Slandering Project MAC (was Slandering Intel)
Message-ID: <57877@linus.UUCP>
Date: 27 Jun 89 12:18:53 GMT
References: <182@mipos3.intel.com> <76700071@p.cs.uiuc.edu> <2126@yunexus.UUCP> <196@uvacs.cs.Virginia.EDU>
Reply-To: munck@faron.UUCP (Robert Munck)
Organization: The MITRE Corporation, Bedford MA
Lines: 14

In <196@uvacs.cs.Virginia.EDU> mac@uvacs.cs.Virginia.EDU (Alex Colvin) writes:
> ...  iNtel can select from 4 (segment registers).
>GE segments were 1^18 words long, iNtel 2^16 bytes.  Therein lies the

A fount of mis- and semi-information.  While I'm not up on machine-language
programming, I believe the 386 has six simultaneous segment selectors --
DS, ES, FS, GS, CS, and SS (last two are code and stack). Also, 16,384
segments are just a tad slower to get to.  True, GE segments were 2^18
(1^18 - typo) (36-bit) words, but be reminded that MULTICS only supported
up to 2^16.  Finally, of course, Intel segments can be up to 2^20 bytes in
byte granularity or 2^20 (4096-byte) pages in page granularity.  The latter
is, of course, 2^32 bytes or 4 gigabytes.
               
                             -- Bob Munck, MITRE