Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!gatech!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: parallel pipelines
Keywords: parallel pipelines
Message-ID: <42151@bbn.COM>
Date: 29 Jun 89 17:57:51 GMT
References: <209@qusunb.queensu.CA>
Sender: news@bbn.COM
Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
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In article <209@qusunb.queensu.CA> levisonm@qucis.queensu.CA (Mark Levison) writes:
>    I have been wondering for a while now why the only pipeline
>designs that I have seen are all sequential.

>    The traditional approach to solving the problem that stage 2 doubles
>the pipeline cycle time is to split it into two stages.

>   But this has two potential problems, first it may not be possible
>to break the original stage 2 into two parts (and thereby increases
>the latency). The second problem is it adds an additional one clock
>cycle buffer delay. So why not create 2 instances of stage 2 and time
>multiplex them.

The Alliant vector processor in the FX/8 does this.  The floating
point multiplier took two clocks for double prec. multiply.  The
reason the multiplier wasn't broken into two parts was because the
chip used the same multiply array twice.  We simply used two of them,
connected in parallel, one for even operands and one for odd.

I don't know of other implementations of this strategy, but that
doesn't mean there aren't any.
-Stan