Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!ames.arc.nasa.gov!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: MIPS/MFLOPS ratio
Message-ID: <27771@ames.arc.nasa.gov>
Date: 29 Jun 89 18:28:15 GMT
References: <596@megatek.UUCP> <140@ssp1.idca.tds.philips.nl>
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Organization: NASA - Ames Research Center
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In article <140@ssp1.idca.tds.philips.nl> roelof@idca.tds.PHILIPS.nl (R. Vuurboom) writes:

>Question is: Is a 3-4 MIPS/MFLOPS balanced?

I personally like a balance of scalar MFLOPS = 1/3 of MIPS and vector MFLOPS =
3* MIPS.  The reasons are manifold, but I have found this to be a "cost 
effective" ratio on older ECL discrete/SSI/MSI vector mainframe systems.  

More recently, folks
in the RISC camp have been saying that this ratio is "obsolete", in the sense
that the "extra" scalar MIPS are almost free relative to the cost of providing
the extra MFLOPS, so a lower ratio is more appropriate.  It appears to me
that MIPSCO is doing about the best that can be done with the new R3xxx chips,
so I am *not* complaining.  But I still think that a vector instruction
set provides a cheap way to get the most out of the existing floating
point real estate, and can improve performance significantly, using the
*same* floating point units, over a machine with only a scalar instruction
set.  Usually a speedup of about 5 is possible in this case, so I would now
like to see MIPS = vector MFLOPS and scalar MFLOPS 1/5 of MIPS.  

For the purpose of comparing microprocessors, I am satisfied to define MIPS 
as the ratio of harmonic means of many integer benchmarks relative to their 
times on a VAX 11/780.  And vector MFLOPS as the time on the standard
LINPACK benchmark.  

Thanks to Weitek, MIPSCO, Fairchild/Intergraph, et al. for raising the 
standard of floating point performance in the micro world.


  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117