Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!srcsip!klemmer!vestal
From: vestal@klemmer.SRC.Honeywell.COM (Steve Vestal)
Newsgroups: comp.arch
Subject: ISA Development Survey
Message-ID: <24852@srcsip.UUCP>
Date: 30 Jun 89 18:55:59 GMT
Sender: news@src.honeywell.COM
Lines: 24

I am interested in getting a better feel for the frequency with which new
instruction set architectures (ISA's) are designed and implemented.  (The ISA
is more or less the description given to a compiler vendor.  Multiple
implementations of the same ISA, e.g. SPARC, do not count.)  I do not want to
limit this to "commercial" applications.  I am interested in anything that
might be considered a programmable processor, including captive development
(e.g., programmable ASIC).

Therefore, I would appreciate hearing of any recent, current, or planned ISA
development work.  Reasonably well-known commercial processors should be
excluded (I can fetch up past postings to comp.arch, too).  If possible,
please characterize as: RISC/CISC/VLIW instruction encoding; degree of
pipelining; and complexity of in-CPU storage (multiple register types, e.g.
data vs. index vs. address; register windows; etc.)  A quiet "I know of
one I'm sure you don't know about" would also be interesting.

As usual, email to me to avoid boring innocent bystanders, and I'll summarize
if I get an interesting enough response (at least for projects that
are not tagged "please don't post info about").  Thanks for your support.

Steve Vestal
Mail: Honeywell S&RC MN65-2100, 3660 Technology Drive, Minneapolis MN 55418 
Phone: (612) 782-7049
ARPA: vestal@src.honeywell.com      UUCP: {mmm, umn-cs, ems}!srcsip!vestal