Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!usc!apple!amdahl!tetons!bb
From: bb@tetons.UUCP (Bob Blau)
Newsgroups: comp.arch
Subject: Re: MIPS Assembler Procedure
Summary: 370 Divide correction
Message-ID: <814@tetons.UUCP>
Date: 30 Jun 89 20:11:14 GMT
References: <812@tetons.UUCP>
Organization: Amdahl Corp., Rexburg, ID
Lines: 20

In article <812@tetons.UUCP>, I write:
> ... it seems that the FORTRAN compiler
> used the D instruction (with the dividend in memory) more often than DR.
> This makes sense, since a memory access out of cache can be considerably
> faster than a double word arithmetic shift right (SRDA). ...

ack - This is irrelevant since both the D and DR insructions have the
dividend in an even odd register pair, so you would need the SRDA in 
either case - sorry for the misinformation.

More to the point perhaps is that the SRDA time is small compared to the
divide time, so the overhead is not too significant, especially given
the rarity of the operation.

			-Bob

-- 
  Bob Blau       Amdahl Corporation    143 N. 2 E., Rexburg, Idaho 83440
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