Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!apple!bionet!ames!ncar!boulder!ccncsu!bizet.CS.ColoState.Edu!rro
From: rro@bizet.CS.ColoState.Edu (Rod Oldehoeft)
Newsgroups: comp.arch
Subject: Re: MIPS/MFLOPS ratio
Message-ID: <2132@ccncsu.ColoState.EDU>
Date: 3 Jul 89 13:25:09 GMT
References: <596@megatek.UUCP> <749@maxim.erbe.se>
Sender: news@ccncsu.ColoState.EDU
Reply-To: rro@bizet.CS.ColoState.Edu.UUCP (Rod Oldehoeft)
Organization: /etc/organization
Lines: 17

In article <749@maxim.erbe.se> rclaeson@erbe.se (Robert Claeson) writes:
>
>A 17 MIPS Motorola 88100 RISC CPU has a fp performance of about 12 MFLOPS.
>That gives (at least) me a MIPS/MFLOPS ratio for that chip of only ~1.4.

I've usually heard MIPS/MFLOPS ratio discussed as the ratio between
the number of instructions (nonFP/FP) actually executed when one
runs an application program of interest.  This is a function of both
the architecture and compiler and is harder to measure than dividing
peak numbers.



Rod Oldehoeft                    rro@handel.CS.ColoState.EDU
Computer Science Department      303/491-5792
Colorado State University
Fort Collins, CO  80523