Xref: utzoo comp.arch:10372 misc.wanted:5344 comp.sources.wanted:7832 Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!ucsd!usc!apple!versatc!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch,misc.wanted,comp.sources.wanted Subject: Re: MIPS Assembler Procedure Message-ID: <22218@winchester.mips.COM> Date: 25 Jun 89 05:08:57 GMT References: <57125@linus.UUCP> <1989Jun24.230056.27774@utzoo.uucp> Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 69 In article <1989Jun24.230056.27774@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes: >In article <57125@linus.UUCP> bs@gauss.UUCP (Robert D. Silverman) writes: >>This, in my opinion is one of the major faults of RISC processors. They >>do not provide basic arithmetic instructions. >When the list of "basic" arithmetic instructions is pages long, one starts >to wonder how many of them are really "basic". The instruction you ask >for -- divide double length by single length yielding single-length result -- >is not exactly frequently needed. Just how much silicon is it worth to make >it run faster than an implementation as a subroutine? Actually, for many languages, on 32-bit machines, use of 32-bit divisor and 64-bit dividend is often worse than useless, especially if it's the only one you have. For example, consider S/360 & followons: 1) The divisor is 64-bits, and must occupy an even-odd register pair. 2) The divide leaves remainder in the even and quotient in the odd. 1) If the dividend (which naturally starts as 32-bits in most cases) is already in an even register (R) is a value not needed any more has an odd-register partner that isn't need any more then you need one instruction, a shift-right-double algebraic (SRDA) to prepare the divisor, i.e., to get: SRDA R,32 DR R,divisor LR result,R (reminder, or R+1 for quotient) 2) If the dividend is in an odd register has a value that should be retained because it's useful later, i.e., J = I/7... use of I has an odd-register partner whose value should be retained then you probably end up generating usage of a scratch register pair: LR RTEMP,R SRDA RTEMP,32 DR RTEMP,divisor LR result,RTEMP (or RTEMP+1, dep. on d 3) Needless to say, the double-register stuff is highly disliked by optimizing compiler writers, as it disrupts the regularity of some of the algorithms; as a result, many compilers end up having to use version 2), at least some of the time. (maybe people current on S/360 architectures might say how often? I'm too rusty to know.) 4) The MIPS sequence is basically what's done by 2) above: div R,divisor ..... other instructions, if compiler can find some and zero-divide check if needed mfhi result (or mflo, to get quotient or remainder) 5) Now, none of this is a terrible deal, as divides aren't that frequent, which is why some RISC architectures omit them entirely. [It depends on which benchmarks you chose whether you think this is good or not.] But note that something that hardware designers might (or might not) think was helping the compiler folks was really getting in their road.... 6) When we were doing this, we couldn't think of any languages whose natural implementation on a 32-bit machine would expect generation of a 64 by 32 bit divide as the expected operation. Does anybody know of any such, or is thsi strictly something one would use in handcoded routines? -- -john mashey DISCLAIMER: UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086