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From: dvadura@watdragon.waterloo.edu (Dennis Vadura)
Newsgroups: comp.sys.m68k
Subject: MC68030 data cache question.
Message-ID: <14803@watdragon.waterloo.edu>
Date: 29 Jun 89 18:00:18 GMT
Reply-To: dvadura@watdragon.waterloo.edu (Dennis Vadura)
Organization: Computer Science Dept., University of Waterloo
Lines: 29

We are in the process of implementing an OS on a system with four 68030
cpu's.  We are having trouble with the 030 data cache during context
switches.  We seem unable to flush the data cache on context switch and obtain
consistent behaviour.  It appears as if some values remain cached after
the context switch.

In addition, the behaviour seems to be dependent on the sequence of
instructions prior to and after the cache reset code.  In some instances it
works and in others it does not, and it appears to be somewhat random,
ie. we have not discovered the reason why a particular sequence works or does
not.

The cache is cleared after changing the page table root pointer
using code that looks like:

	movl 0x909, %d0
	movl %d0, %cacr

Does anyone have any experience with using the data cache?  Code, comments,
speculation are all welcome.  If you need more info send mail.

NOTE:  We have no problem with the instruction cache.

-dennis
-- 
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Death is an experience that is best    |Dennis  UUCP,BITNET:    dvadura@water
shared.  [Lt. Worf]                    |Vadura  EDU,CDN,CSNET:  dvadura@waterloo
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