Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!apple!usc!polyslo!ttwang
From: ttwang@polyslo.CalPoly.EDU (Thomas Wang)
Newsgroups: comp.arch
Subject: Micro-pipeline paper
Message-ID: <12362@polyslo.CalPoly.EDU>
Date: 7 Jul 89 20:08:42 GMT
Reply-To: ttwang@polyslo.CalPoly.EDU (Thomas Wang)
Distribution: usa
Organization: Cal Poly State University -- San Luis Obispo
Lines: 16

In this month's Communiction of ACM there is an interesting paper on
Micro-pipelines and transitional logic.  I found its ideas to be revolutional.

This is a VLSI design philosophy that eliminates the need for clocks.  All
components are self synchronized, making modular replacement and improvement
possible.

A silicon compiler for Micro-pipeline machines should be easier, since the
interactions between components all follow a standard protocol.


 -Thomas Wang (Mak-Kuro Kurosuke, come on out!  If you don't come out,
               we'll pull your eyeballs out!
                                      - as heard in Tonari No Totoro )

                                                     ttwang@polyslo.calpoly.edu