Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!vsi1!wyse!stevew
From: stevew@wyse.wyse.com (Steve Wilson xttemp dept303)
Newsgroups: comp.arch
Subject: Re: Double Width Integer Multiplication and Division
Message-ID: <2281@wyse.wyse.com>
Date: 7 Jul 89 19:45:42 GMT
References: <1035@aber-cs.UUCP> <1370@l.cc.purdue.edu> <2274@wyse.wyse.com> <3243@alliant.Alliant.COM>
Sender: news@wyse.wyse.com
Reply-To: stevew@wyse.UUCP (Steve Wilson xttemp dept303)
Organization: Wyse Technology
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In article <3243@alliant.Alliant.COM> lewitt@Alliant.COM (Martin E. Lewitt) writes:
>I'm not sure what machines out there are giving you the impression that
>VLIW assembly is difficult, but that wasn't my experience at all.  I found
> stuff deleted...

The Cydra-5.  I worked on this hardware directly and have a fair idea 
of the complexity for that specific architecture.  Things are easy
enough when your running linear code, but when you have 4 interations
of the same loop hot at the same time, and each resource is involved
with a different interation during the same clock, and how do you 
deal with the register allocation such that you don't cause the various
interations to colide with each other, i.e. don't break the dependencies,
etc.  It just gets worse from here, i.e. my hats off to the compiler
guys that could get this thing to run!

Steve Wilson