Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!ames!elroy.jpl.nasa.gov!ucla-cs!frazier
From: frazier@oahu.cs.ucla.edu (Greg Frazier)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <25547@shemp.CS.UCLA.EDU>
Date: 8 Jul 89 00:48:44 GMT
References: <13976@lanl.gov>
Sender: news@CS.UCLA.EDU
Reply-To: frazier@cs.ucla.edu (Greg Frazier)
Organization: UCLA Computer Science Department
Lines: 51

In article <13976@lanl.gov> jlg@lanl.gov (Jim Giles) writes:
>Every once in a while, someone in this newsgroup makes the claim
>that RISC trades off hardware complexity for compiler complexity.
>This is simply _NOT_ true.  It is always _easier_ to write a compiler
>for a RISC machine than for a CISC machine.
>
[ deleted explanation of compiler front- and backend ]
>For a RISC machine, the only hard part of the "back end" is register
>allocation.  Instruction selection is fairly simple since there is
>generally only one way the perform each intermediate code operation.
>On a pipelined machine, code ordering comes into play (at least if
>you want optimized code).  This compilcates matters, since a different
>code ordering makes different register allocation constraints.
>For this reason, optimizing can be difficult, even on a RISC machine.
>
>On a CISC machine, instruction selection can be a real problem.  This
>is because there are generally several instruction sequences possible
>to implement each operation.  Instruction selection obviously
>effects the register allocation phase (and the code ordering phase).  
>To make matters worse, instruction selection is context sensitive.
>This means that different code ordering during optimization could
>invalidate the instruction selection choice (or, at least make the
>selected instructions sub-optimal).
>
>There may indeed be a trade off between RISC and CISC.  But this
>trade off is certainly _not_ in the complexity of the compiler.
>In fact, as shown above, the circumstance is quite the opposite.

Actually, I believe you are wrong, Jim.  While code selection
is easier on a RISC, CISC compilers tend to avoid this by only
using the simple compilers.  On the other hand, RISCs require
very good optimizers in order to take advantage of their RISC-ness.
This is complex.  In addition, most RISC architectures expose their
pipelines, and hence require the compiler to avoid interlocks,
etc.  This is also complex.  On a related note, RISCs tend to
have delayed branches, register windows, etc. which the compiler
must understand.  Finally, as you pointed out, RISCs require
sophisticated register allocation.

So, you are right, in that the reduced instruction set makes
instruction selection much simpler.  So I guess it is easier to
write a stupid compiler for a RISC.  However, because a generic 
RISC arch allows and requires a high level of optimization,
they end up being very complex.

Greg Frazier
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