Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!bbn!gatech!amdcad!crackle!tim
From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <26247@amdcad.AMD.COM>
Date: 9 Jul 89 18:00:35 GMT
References: <13976@lanl.gov> <25547@shemp.CS.UCLA.EDU>
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Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc. Sunnyvale CA
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In article <25547@shemp.CS.UCLA.EDU> frazier@cs.ucla.edu (Greg Frazier) writes:
| Actually, I believe you are wrong, Jim.  While code selection
| is easier on a RISC, CISC compilers tend to avoid this by only
| using the simple compilers.  On the other hand, RISCs require
| very good optimizers in order to take advantage of their RISC-ness.

No, RISCs don't *require* very good optimizers; they just make it easier
to perform some optimizations.  Very simple compilers can be used with
fairly good results.

| This is complex.  In addition, most RISC architectures expose their
| pipelines, and hence require the compiler to avoid interlocks,
| etc.  This is also complex.

*Most* RISC architectures?  The Stanford MIPS processor did not have
interlocks, but nearly all other RISC processors do (a recent exception
is the i860, which exposes the pipeline in pipelined floating-point mode).


| On a related note, RISCs tend to
| have delayed branches, register windows, etc. which the compiler
| must understand.

I would claim that the stack-cache operation of the Am29000 register
file is *easier* to generate code for than a standard register file. 
Just determine the maximium number of registers required by a function
and allocate them on function entry -- register spilling & filling is
taken care of automatically by bounds checks.  Yes, delayed branches
have to be taken care of, but they aren't particularly hard -- some
systems don't put this in the compiler; it is done at assembly or link
time, along with other optimizations.

| Finally, as you pointed out, RISCs require
| sophisticated register allocation.

No, it is just useful to help reduce memory traffic.



	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)