Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!sun-barr!newstop!sun!gammara!khb
From: khb@gammara.Sun.COM (gammara)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <114448@sun.Eng.Sun.COM>
Date: 10 Jul 89 00:24:39 GMT
References: <13976@lanl.gov>
Sender: news@sun.Eng.Sun.COM
Reply-To: khb@sun.UUCP (gammara)
Organization: Sun Microsystems, Mountain View
Lines: 27

In article <13976@lanl.gov> jlg@lanl.gov (Jim Giles) writes:
>This is simply _NOT_ true.  It is always _easier_ to write a compiler
>for a RISC machine than for a CISC machine.
>
> stuff about compilers

Well, if RISC machines were simple (everyting in 1 cycle, no
overlapped execution, sans multiple functional units, etc.) you would
be 100% right.

Unfortunately RISC is commonly applied to machines like SPARC, MIPSco,
i860 and others.

It is said that Metaflow is working on a SPARC with several functional
units, for example.

Even for the current chips employed by Sun, instruction scheduling is
one of the most interesting optimizations (wrt effectiveness on real
programs). On a machine such as Metaflow is working on, instruction
scheduling could become as interesting as a TRACE/28 ....

Such compilers are NOT simpler than CISC compilers.

Keith H. Bierman      |*My thoughts are my own. Only my work belongs to Sun*
It's Not My Fault     |	Marketing Technical Specialist    ! kbierman@sun.com
I Voted for Bill &    |   Languages and Performance Tools. 
Opus  (* strange as it may seem, I do more engineering now     *)