Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!uunet!daitc!daitc.daitc.mil
From: jkrueger@daitc.daitc.mil (Jonathan Krueger)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <582@daitc.daitc.mil>
Date: 10 Jul 89 05:44:26 GMT
References: <13976@lanl.gov>
Sender: news@daitc.daitc.mil
Reply-To: jkrueger@daitc.daitc.mil (Jonathan Krueger)
Organization: DTIC Special Projects Office (DTIC-SPO), Alexandria VA
Lines: 15
In-reply-to: jlg@lanl.gov (Jim Giles)

In article <13976@lanl.gov>, jlg@lanl (Jim Giles) writes:
>Every once in a while, someone in this newsgroup makes the claim
>that RISC trades off hardware complexity for compiler complexity.
>This is simply _NOT_ true.  It is always _easier_ to write a compiler
>for a RISC machine than for a CISC machine.

False.  It is always easier to generate code for a simple, orthogonal
instruction set.  (Corollary: it is always easier to generate optimal
code for a simple, orthogonal instruction set with simple, regular
rules for timings.)  The belief that every RISC machine exhibits these
characteristics more than any CISC is not based on fact.

-- Jon
-- 
--