Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <1989Jul11.155320.23738@utzoo.uucp>
Organization: U of Toronto Zoology
References: <2190@oakhill.UUCP> <13980@lanl.gov>
Date: Tue, 11 Jul 89 15:53:20 GMT

In article <13980@lanl.gov> jlg@lanl.gov (Jim Giles) writes:
>> What about the required pairing of registers for double wide operations
>> such as floating-point or shifting? 
>
>In what way does a machine which requires register pairing qualify as
>a RISC?  ...

Don't be too hard on the guy; he's judging all RISCs by the lousy one he's
got.  Only Motorola could build a RISC with register pairing... :-)

>... If you are not using those
>extra instructions, you might as well have a RISC which provides
>only the instructions you _do_ use.  The hardware designer could
>then spend more time making those work faster...

In fact, it is notoriously true that many CISCs run faster if the compiler
writer treats them as RISCs and ignores all the fancy stuff.

>...RISC machines are easier to pipeline, easier to speed up the clock
>for, easier to provide staged functional units for, etc..  I don't
>know of any CISC machines with 'hardwired' instruction sets...

I can think of a couple of old ones.  The first pdp11, the 11/20, was
hardwired.  (This accounts for some of the little irregularities in the
11 instruction set, in fact, like the way INC isn't quite the same as
ADD #1...)  And I seem to recall that the 360/75 was mostly hardwired,
for speed.
-- 
$10 million equals 18 PM       |     Henry Spencer at U of Toronto Zoology
(Pentagon-Minutes). -Tom Neff  | uunet!attcan!utzoo!henry henry@zoo.toronto.edu