Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!gatech!cica!tut.cis.ohio-state.edu!cs.utexas.edu!oakhill!davet
From: davet@oakhill.UUCP (David Trissel)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <2199@oakhill.UUCP>
Date: 11 Jul 89 10:24:06 GMT
References: <2190@oakhill.UUCP> <13980@lanl.gov>
Reply-To: davet@oakhill.UUCP (David Trissel)
Organization: Motorola Inc., Austin Tx.
Lines: 67

In article <13980@lanl.gov> jlg@lanl.gov (Jim Giles) writes:

>> What about the required pairing of registers for double wide operations
>> such as floating-point or shifting? 

>In what way does a machine which requires register pairing qualify as
>a RISC?  

The point was that RISC architectures DO require the pairing. Can you name
any that don't?

>If an instruction requires 2 operands, they should be allowed
>to be any two general purpose registers. 

This is not what was being discussed.

>Furthermore, you are assuming
>that floating point is larger than other intrinsic types. 

Well, unless you limit yourself to only single-precision, floating-point IS
larger than other instrinsic types.

>The best RISCs are those which only have _one_ data size. 

Such an architecture would utterly fail in the marketplace. This is so far
off base it doesn't need a rebuttal.

>(By the way, my model of a reasonable RISC would be a Cray-I instruction 
>set without vectors.  This is certainly RISCy - all data is 64 bits, all 
>operations are reg to reg, only one memory addressing mode, etc..)

Do you have any inkling why your ideas aren't being implemented by RISC 
designers?

>So, this issue _does_ have a bearing on the complexity of the compiler.
>If you are not willing to provide the sophisticated compilers required
>to adequately use a machine, you have wasted money (read: design effort,
>chip space, etc.) on the hardware.

Nope, no bearing on the compiler. There is no gun being pointed at the compiler
writer forcing her to utilize all the available instructions. Your assumption
that most of the instructions have to be used "to adequately use a machine"
is simply incorrect.

>All the optimizations required on a RISC are also required on a CISC.  

Wrong. 68K compilers don't have to worry about register pairing. 68K compilers
don't have to worry about branch delayed slot filling, setting up segment
registers for data addressability, etc.

>CISC just adds more complexity to the mix.

I showed otherwise in that RISC has it's own set of headaches. I don't see
much difference in the total amount of work involved for either RISC or
CISC.

>Now, clearly 5 instructions may take longer than the 1 in your 68K example.

Actually RISCs only require 2 or 3 instructions to do the work of
the one in that example.

>All this may mean that 5 instructions on a RISC may be _faster_ than one 
on a CISC.

Not when using the latest CISCs.

 -- Dave Trissel  Motorola Austin