Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!bionet!ames!apple!sun-barr!newstop!pitstop!acockcroft
From: acockcroft@pitstop.West.Sun.COM (Adrian Cockcroft)
Newsgroups: comp.arch
Subject: Re: MIPS/MFLOPS ratio [long; here we go again; sorry]
Message-ID: <748@pitstop.West.Sun.COM>
Date: 11 Jul 89 12:51:52 GMT
References: <596@megatek.UUCP> <112807@sun.Eng.Sun.COM> <114015@sun.Eng.Sun.COM>
Organization: Sun Microsystems, Mt. View, CA
Lines: 54


There was a call for some cycle time summaries for SPARC FPU's and khb
didn't have time to provide them. I happen to have a summary online so
here it is.

The Weitek ABACUS 3170 is a LSI/Fujitsu compatible SPARC FPU which uses the
F-bus to hang off the side of the IU. It runs at 25 MHz only. As used in SS1.

The Weitek ABACUS 3171 is a Cypress compatible SPARC FPU which picks up
its operands in parallel to the IU. It runs at 25, 33 and 40 MHz.

Once the FP instructions have been despatched (I think 2 cycles on Fujitsu
and 1 cycle on Cypress) the performance is the same.

I compare below with data taken from the CY7C609 FPC (with TI8847) data sheet
For Linpack comparisons the 8847 is about 1.5 DP MFLOPS and the 3170 is about
1.36 DP MFLOPS in a SS1 (20 MHz). Some early SS1's were fitted with 8847's on
daughter boards, it's not an option because its much more expensive than
the 3170 for a marginal improvement.

I'm not sure how much pipelineing takes place inside each FPU, these cycles
are for a single instruction from start to finish.

Adrian

Instruction  3170 cycles    TI8847 cycles
fitos		10		8
fitod		5		8
fstoi		5		8
fdtoi		5		8
fstod		5		8
fdtos		5		8
fmovs		3		8
fnegs		3		8
fabss		3		8
fsqrts		60		15
fsqrtd		118		22
fadds		5		8
faddd		5		8
fsubs		5		8
fsubd		5		8
fmuls		5		8
fmuld		8		9
fdivs		38		13
fdivd		66		18
fcmps		3		8
fcmpd		3		8
fcmpes		3		8
fcmped		3		8


-- 
Adrian Cockcroft Sun Cambridge UK TSE sun!sunuk!acockcroft
Disclaimer: These are my own opinions