Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!iuvax!cica!tut.cis.ohio-state.edu!pt.cs.cmu.edu!andrew.cmu.edu!zs01+ From: zs01+@andrew.cmu.edu (Zalman Stern) Newsgroups: comp.arch Subject: Re: Register pairing (Was: Compiling - RISC vs. CISC) Message-ID: Date: 11 Jul 89 16:35:31 GMT References: <2190@oakhill.UUCP> <13980@lanl.gov>, <2199@oakhill.UUCP> Organization: Information Technology Center, Carnegie Mellon, Pittsburgh, PA Lines: 41 In-Reply-To: <2199@oakhill.UUCP> As with all arguments about RISC vs. CISC, the latest compiler complexity argument is bogus because RISC and CISC are hardly monolithic categories. That is, there are characteristics that lean toward one camp or another and various chips use different combinations of these characteristics. Anyway, I would like some clarification on one specific point: > Excerpts from ext.nn.comp.arch: 11-Jul-89 Re: Compiling - RISC vs. CISC > David Trissel@oakhill.UU (2486) > The point was that RISC architectures DO require the pairing. Can you > name > any that don't? By "register pairing" I assume you mean instructions which take an even register specification and use the adjacent odd register as well. My perusal of the MIPS R2000 book indicates that there are no such instructions in that architecture. I believe this is also true of the AMD 29000. I think its almost true of the SPARC, but it has 64 bit load and store instructions from the integer unit's register file that utilize register pairing. (As I understand it the main reason these instructions were added to the SPARC was to speed up transferring register windows to/from memory. It is probably reasonable to write a compiler for SPARC that ignores these instructions and doesn't have to worry about register pairing.) The only place I could find register pairing in the 88000 was in the floating point instructions. This is a result of using one register file for the integer and floating point units. (My knowledge of the 88000 is limited, I have the user's manual, but I haven't read it in depth. I may be wrong about this...) Most other "RISC" chips I know of have separate integer and floating point register sets and avoid this problem. If my understanding of register pairing is incorrect, could you please post a correct definition. Also explain where this is going to come up in register allocation for a machine like the MIPS R2000. Sincerely, Zalman Stern Internet: zs01+@andrew.cmu.edu Usenet: I'm soooo confused... Information Technology Center, Carnegie Mellon, Pittsburgh, PA 15213-3890