Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!cbmvax!daveh
From: daveh@cbmvax.UUCP (Dave Haynie)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <7259@cbmvax.UUCP>
Date: 11 Jul 89 15:33:16 GMT
References: <13980@lanl.gov>
Organization: Commodore Technology, West Chester, PA
Lines: 39

in article <13980@lanl.gov>, jlg@lanl.gov (Jim Giles) says:

> From article <2190@oakhill.UUCP>, by davet@oakhill.UUCP (David Trissel):
>> In article <13976@lanl.gov> jlg@lanl.gov (Jim Giles) writes:
>>    mov.l  (%an),%dn
>>    add.l  &4,%an
>> or the faster
>>    mov.l  (%an)+,%dn
>> The 68K requires a routine in the compiler peephole optimizer to "discover" 
>> and implement this optimization. But the result is a single 16-bit instruction
>> which (I think) executes in a single clock on the MC68040.

> Now, clearly 5 instructions may take longer than the 1 in your 68K example.
> But, RISC machines are easier to pipeline, easier to speed up the clock
> for, easier to provide staged functional units for, etc..  I don't
> know of any CISC machines with 'hardwired' instruction sets.  

That's probably why the 68040 was mentioned in the original example.  It has a
decent number of hardwired instructions, thus the aforementioned move with
post increment executes in one _clock_ (at least I had the same recollection;
many of the instructions execute in a single clock).  You're going to be hard
pressed to make a RISC do better than one instruction/clock (some do by 
exploiting parallel execution units, a concept not limited to RISC), and if your
RISC machine needs more instructions to achieve the same result, you lose. 
The main advantage any RISC is going to have in the long run is its 
simplicity.  A thing like the 68040 can adopt many if not all of the tricks 
you'll find in RISC machines, but it's a very large processor, and you're 
probably not going to see it in ECL or GaAs anytime soon.  Its CMOS process 
is probably not good for much over 50MHz (top speed on the 68030 anyway).  
Folks are talking about ECL designs starting at 60MHz-80MHz and continuing on 
with GaAs into the 100MHz to 200MHz range.  The first CPUs that get there will
be extremely simple ones so that the number of chips (and thus slow external 
connections) can be kept to a minimum.  And so they can be made in the first
place with the very latest technologies, which aren't counting millions of
transistors yet.
-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: D-DAVE H     BIX: hazy
           Be careful what you wish for -- you just might get it