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From: frazier@oahu.cs.ucla.edu (Greg Frazier)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC (exposed pipelines)
Message-ID: <25619@shemp.CS.UCLA.EDU>
Date: 11 Jul 89 17:45:54 GMT
References: <13976@lanl.gov> <25547@shemp.CS.UCLA.EDU> <26247@amdcad.AMD.COM> <25562@shemp.CS.UCLA.EDU> <26257@amdcad.AMD.COM> <151@ssp1.idca.tds.philips.nl>
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Reply-To: frazier@cs.ucla.edu (Greg Frazier)
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In article <151@ssp1.idca.tds.philips.nl> roelof@idca.tds.PHILIPS.nl (R. Vuurboom) writes:
>
>This term has been confusing me (too?). Is this the (an?) "accepted"
>definition of exposed pipeline?

My understanding is that an exposed pipeline is one in which
interlocks, register reservations, etc. are done in software.
Thus, if you have a 10 cycle divide and a 2 cycle addition,
and have in your machine code
R1 <- R2 / R3
R4 <- R1 + R2,
you are going to get an incorrect value in R4, unless you
stick a bunch of no-ops inbetween.  In an un-exposed pipeline,
the compiler does not have to know how long operations take,
the hardware performs register reservations and prevents such
things from happening.  Thus, in my second posting, the
question as to the applicability of discussing exposed/unexposed
pipelines in the context of a RISC, even though I was the one
who brought it up in the first place.  Yes, I'm a bit of a
chuckle-head :-)

Greg Frazier
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