Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!uunet!mcvax!dik
From: dik@cwi.nl (Dik T. Winter)
Newsgroups: comp.arch
Subject: Re: More RISC vs. CISC wars
Message-ID: <8263@boring.cwi.nl>
Date: 12 Jul 89 00:15:14 GMT
References: <42550@bbn.COM> <13982@lanl.gov>
Organization: CWI, Amsterdam
Lines: 30

In article <13982@lanl.gov> jlg@lanl.gov (Jim Giles) writes:
 > From article <42550@bbn.COM>, by slackey@bbn.com (Stan Lackey):
 > < For example, the Alliant executes the instruction:
 > <
 > < 	add.d  (an)+, fp0
Nonsense.  It is either
	addd	(an)+,d0
or
	faddd	(an)+,fp0
 > < 
 > < in one cycle (yes, that's double precision memory-to-register add,
 > < auto increment), and it's microcoded.
 > 
 > And, how many microcycles does 'one cycle' on the Alliant correspond
 > to?

I do not know about microcycles, but seeing that the cycle time on the
Alliant is 170 nsec. it is clear that one cycle execution is required
to get any performance.  And, yup, the Alliant will outperform the
SPARCstation 1 by a factor of up to 20 on some benchmarks, but if you
try to compile something the Alliant is clearly inferior.
(I have just been doing some benchmarking, a SPARC: 1.5 Megaflop single
precision; Alliant: up to 30 (4 processor FX4).  Compilation: SPARC at
least 2.5 times as fast.)

Moral: use the tool you have at hand to do the task you have at hand.
-- 
dik t. winter, cwi, amsterdam, nederland
INTERNET   : dik@cwi.nl
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