Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!haven!uvaarpa!babbage!mac3n
From: mac3n@babbage.acc.virginia.edu (Alex Colvin)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Summary: Honeywell easy register allocation
Keywords: CISC, vCISC, compiler
Message-ID: <745@babbage.acc.virginia.edu>
Date: 12 Jul 89 17:55:16 GMT
References: <13976@lanl.gov> <2613@yunexus.UUCP>
Organization: University of Virginia
Lines: 36

>   The Honeywell (now Bull) DPS-8 is a conscious attempt at a
> very-complex-instruction set computer, based on the basic architecture
> of the era of IBM 7090s and DEC-10s.

> .... Given a compiler (say, FORTRAN
> IV) for the basic machine language, one can add all the constructs for
> PL/1 and (you should pardon the expression) COBOL to your language in
> about two man-days: Honeybun put the primitives into the EISbox
> (Extended Instruction Set).

>   The machine is still in production, is still very CISC, and actually
> runs rather well.  They really did "narrow the semantic gap between
> the machine language and the language understood by the compiler",
> which was the reason d'etre of the vCISC machines.

Only for some languages.  PL/I, COBOL.  Try C.  While the machine does
understand character strings, it doesn't understand single characters very
well.  They're pretty much restricted to the EIS instructions, which are
strictly memory-memory, in contrast to the rest of the instruction set,
which is memory-register.

>   One can even generate good code for them (;-)), because they're
> either regular, or only exist in one variant.

Sure, it's easy to do optimal register allocation when all you've got is one
good register (EAQ).

>  Mind you, I can't recommend the underlying order code (the stuff that
> preceded the EISbox) to my worst enemy.  The machine is a sorta wart
> with an elegant bag on the side.

"Order code" gives you an idea of the age of the basic architecture.  But
EIS is a mess.  Seriously, I grew up on this machine, and I can say that I
prefer i80*86s.  Perhaps I'm biased by the early flaky implementations of
EIS (such as 0-length string copy faulting) and the wild variation in
instruction timing among different models.