Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!uunet!dg!rec
From: rec@dg.dg.com (Robert Cousins)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <199@dg.dg.com>
Date: 10 Jul 89 13:23:34 GMT
References: <13976@lanl.gov>
Reply-To: uunet!dg!rec (Robert Cousins)
Organization: Data General, Westboro, MA.
Lines: 36

In article <13976@lanl.gov> jlg@lanl.gov (Jim Giles) writes:
>Every once in a while, someone in this newsgroup makes the claim
>that RISC trades off hardware complexity for compiler complexity.
>This is simply _NOT_ true.  It is always _easier_ to write a compiler
>for a RISC machine than for a CISC machine.

>In fact, as shown above, the circumstance is quite the opposite.

I must agree.  Our experience on the 88K with a number of pieces 
of software from gcc to an internally developed FORTH interpreter 
has shown that RISCs are easier to generate code for.  I would 
carry this a step further.  While the assembly language development 
effort is minimal, we have had little difficulty with assembly 
language to the point where I wonder if RISCs might not be easier 
to program at that level, also.  If a programmer can do it easily . . . .

Concerning your optimization comment, I would like to throw out an
interesting phenomenon we have noticed (perhaps other RISCers will
comment also):  At one point, people were talking about RISC processors
needing to execute MORE instructions to do the same amount of work.
THis implied that where a CISC might require 100 instructions, a
RISC might require >100 instructions, though the RISC instructions
would take less time.  We have noticed that in many cases, the 
instruction count goes down.  In fact, the best example is the
Dhrystone benchmark.  Since Dhrystone is an artificial measure of
integer compute power, a "Dhrystone MIPS" is considered one VAX MIPS
of compute power.  On the 88K, we need less than 1 MIPS to generate
a Dhrystone MIPS.  In other words, we get Dhrystone MIPS > CPU
clock speed.  When this first happened here, many people were
mumbling about clocks running backward and Escher paintings . . . . :-)

Robert Cousins
Dept. Mgr, Workstation Dev't.
Data General Corp.

Speaking for myself alone.