Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!apple!agate!ucbvax!hplabs!hp-ses!hpcuhb!hpihoah!fotland
From: fotland@hpihoah.HP.COM (Dave Fotland)
Newsgroups: comp.arch
Subject: Re: Re: Compiling - RISC vs. CISC (exposed pipelines)
Message-ID: <4420014@hpihoah.HP.COM>
Date: 12 Jul 89 16:20:52 GMT
References: <13976@lanl.gov>
Organization: Hewlett Packard, Cupertino
Lines: 28

> davet@oakhill.UUCP (David Trissel) writes:
>In article <13980@lanl.gov> jlg@lanl.gov (Jim Giles) writes:
>
>>> What about the required pairing of registers for double wide operations
>>> such as floating-point or shifting? 

>>In what way does a machine which requires register pairing qualify as
>>a RISC?  

>The point was that RISC architectures DO require the pairing. Can you name
>any that don't?

Hewlett Packard precision architecture doesn't require register pairing.
Double shifts can use any two general registers.  The floating point
registers are separate from the general registers and each can hold either
a 32 bit or 64 bit floating point value.  The compiler writers were against
requiring pairing and the floating point experts felt that double precision
was more important than single so there was no need to try to put two
singles in a double precision register.  This is also why double precision
floating point is only slightly slower than single on most HP-PA machines.

Floating point operations are naturally slower than integer operations
so it makes sense to have them handled by a coprocessor so they can overlap
with integer operations.  Having separate floating point registers makes
the coprocessor design easier and saves communication between the IU and FPU.

David Fotland
fotland@hpda.hp.com