Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!bionet!ames!hc!lanl!jlg
From: jlg@lanl.gov (Jim Giles)
Newsgroups: comp.arch
Subject: Re: More RISC vs. CISC wars
Message-ID: <13984@lanl.gov>
Date: 12 Jul 89 23:43:18 GMT
References: <42621@bbn.COM>
Organization: Los Alamos National Laboratory
Lines: 22

From article <42621@bbn.COM>, by slackey@bbn.com (Stan Lackey):
> In article <13982@lanl.gov> jlg@lanl.gov (Jim Giles) writes:
>>And, how many microcycles does 'one cycle' on the Alliant correspond
>>to?  
> 
> One.  The reason many, even memory-to-register, operations take one
> microcycle is because it has a scalar pipeline.  Even though pipelines
> "can't-be-done" on CISC's.

You are either using pipelines (in which case the instruction _issues_
in one clock, but the result is not delivered for several more), or
you aren't (in which case, I don't believe your claim that the instruction
has no microcycles).  RISCs can also be pipelined (easier than CISCs),
and the several simple instructions may execute as fast or faster than
the one big one.  And (back to the original subject), it is easier to 
_compile_ for a RISC machine.

Now that you've said that the Alliant is pipelined, you have to tell
be what the _real_ instruction timing for the given example is.  What
is the minimum number of clocks between issuing the given instruction
and issuing the next instruction which uses one of the results of the
one given?  Bet it ain't 1.