Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!cmcl2!lanl!jlg
From: jlg@lanl.gov (Jim Giles)
Newsgroups: comp.arch
Subject: Re: More RISC vs. CISC wars
Message-ID: <13985@lanl.gov>
Date: 12 Jul 89 23:59:31 GMT
References: <42621@bbn.COM>
Organization: Los Alamos National Laboratory
Lines: 19

From article <42621@bbn.COM>, by slackey@bbn.com (Stan Lackey):
> [...]
> As I hope I clarified above, the pipeline allows a very long sequence
> of operations, including a memory access, to consume effectively one
> cycle of execution time.  Specifically, memory-to-register floating
> point takes six cycles from front to back, but with the pipeline
> really consumes only one cycle.

Or it really consumes six!!  Depends upon whether there is anything
independent to do while this instruction runs.  If the next instruction
depends on the result of this one, the next gets delayed six clocks. Period.

With a RISC instruction set, you can move the individual components of
this complex "instruction" around to get maximum overlap from your pipeline.
Splitting the functionality of the instruction requires more instruction
issues, but it also allows better flexibility in instruction scheduling
optimizations.  It would require a _very_ smart compiler to tell which
way to go.  This is exactly one of the points I made originally about
CISCs being harder to compile for.