Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!apple!ames!ames.arc.nasa.gov!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <28471@ames.arc.nasa.gov>
Date: 13 Jul 89 01:40:18 GMT
References: <13976@lanl.gov> <199@dg.dg.com>
Sender: usenet@ames.arc.nasa.gov
Organization: NASA - Ames Research Center
Lines: 17

In article <199@dg.dg.com> uunet!dg!rec (Robert Cousins) writes:
>of compute power.  On the 88K, we need less than 1 MIPS to generate
>a Dhrystone MIPS.  In other words, we get Dhrystone MIPS > CPU
>clock speed.  When this first happened here, many people were

Could you clarify what you mean? I know of no correlation between
"Dhrystones/second" and "Instructions issued/second".

Also, on a lot of machines, the Dhrystone rating is quite a bit higher
than a simple "MIPS"/"VAX MIPS" ratio would indicate, thus demonstrating
that Dhrystone is but one of many benchmarks, and the 11/780 does better
on others...

  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117