Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!sharkey!atanasoff!hascall
From: hascall@atanasoff.cs.iastate.edu (John Hascall)
Newsgroups: comp.arch
Subject: Re: More RISC vs. CISC wars
Message-ID: <1200@atanasoff.cs.iastate.edu>
Date: 13 Jul 89 01:09:37 GMT
References: <42621@bbn.COM> <13985@lanl.gov>
Reply-To: hascall@atanasoff.cs.iastate.edu.UUCP (John Hascall)
Organization: Iowa State Univ. Computation Center
Lines: 18

In article <13985@lanl.gov> jlg@lanl.gov (Jim Giles) writes:
 
>From article <42621@bbn.COM>, by slackey@bbn.com (Stan Lackey):
>> [...]
>>                        Specifically, memory-to-register floating
>> point takes six cycles from front to back, but with the pipeline
>> really consumes only one cycle.
 
>Or it really consumes six!!  Depends upon whether there is anything
>independent to do while this instruction runs.  If the next instruction
>depends on the result of this one, the next gets delayed six clocks. Period.
 
   I doubt it is delayed all six, surely the first part of the next
   instruction can be done (at least the fetch and decode).


   John Hascall
   ISU Comp Center