Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!ucsd!usc!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <42682@bbn.COM>
Date: 13 Jul 89 14:20:29 GMT
References: <13976@lanl.gov> <199@dg.dg.com>
Sender: news@bbn.COM
Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
Lines: 15

In article <199@dg.dg.com> uunet!dg!rec (Robert Cousins) writes:
>Concerning your optimization comment, I would like to throw out an
>interesting phenomenon we have noticed (perhaps other RISCers will
>comment also):  At one point, people were talking about RISC processors
>needing to execute MORE instructions to do the same amount of work.
>THis implied that where a CISC might require 100 instructions, a
>RISC might require >100 instructions, though the RISC instructions
>would take less time.  We have noticed that in many cases, the 
>instruction count goes down.  

I assume you mean 'instruction count goes down relative to our old
architecture'.  I bet going from 4 to 30 registers did something for
register spills and lots of other interesting stuff...  As well as
byte addressability...
:-) Stan