Path: utzoo!bnr-vpa!bnr-fos!bnr-public!schow
From: schow@bnr-public.uucp (Stanley Chow)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <747@bnr-fos.UUCP>
Date: 14 Jul 89 01:45:30 GMT
References: <199@dg.dg.com> <28471@ames.arc.nasa.gov> <200@dg.dg.com>
Sender: news@bnr-fos.UUCP
Reply-To: schow%BNR.CA.bitnet@relay.cs.net (Stanley Chow)
Organization: Bell-Northern Research, Ottawa, Canada
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In article <200@dg.dg.com> uunet!dg!rec (Robert Cousins) writes:
>
>Hugh, I agree that Dhrystone is one benchmark in a whole field of
>benchmarks.  However, I feel comfortable drawing a simple conclusion
>from this result:  It is not clear that a CISC processor will take
>FEWER INSTRUCTIONS to solve a problem than a RISC processor.  In some
>cases RISCs may require fewer instructions.
>

This is such a simple issue that arguing is pointless. You can just
post the static and dynamic instruction counts for some sample CPU's
and settle the question.

Static numbers ought to be easy to get. Dynamic numbers can be either
true dynamic number or just approximation by counting inner loops.
Since you are making a "suprising" claim, you ought to come up with
the numbers.



Stanley Chow        BitNet:  schow@BNR.CA
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