Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!apple!sun-barr!newstop!pitstop!acockcroft
From: acockcroft@pitstop.West.Sun.COM (Adrian Cockcroft)
Newsgroups: comp.arch
Subject: Re: Compiling - RISC vs. CISC
Message-ID: <764@pitstop.West.Sun.COM>
Date: 14 Jul 89 12:39:09 GMT
References: <13976@lanl.gov> <199@dg.dg.com>
Organization: Sun Microsystems, Mt. View, CA
Lines: 25

> In other words, we get Dhrystone MIPS > CPU
> clock speed.  When this first happened here, many people were
> mumbling about clocks running backward and Escher paintings . . . . :-)
> 
> Robert Cousins

I'm interested to see what code the compiler produced for the 88k
could you mail me your Dhrystone source code and the resultant
assembler output (cc -S on sun). I'll compile your source and compare it
to the SPARC equivalent to try to see what optimisations have been
performed. I can also run the SPARC dhrystone through SPARCsim to
get an instruction mix analysis. If I get anywhere I will post the results
back here.

As an aside, I used to use the Greenhills 68k C compiler a lot for
realtime work and I found that the compiler optimisations were
style dependent. I eventually found what sort of expressions the
compiler could cope with best by tweaking the C code and looking
at the assembler produced. In particular strength reduction
optimisations were very dependent on the way I wrote loops.


-- 
Adrian Cockcroft Sun Cambridge UK TSE sun!sunuk!acockcroft
Disclaimer: These are my own opinions